High-temperature ovens, called reactors, are used to create structures of very fine dimensions, such as integrated circuits on semiconductor substrates. One or more substrates, such as silicon wafers (which may or may not include previously formed structures thereon or therein), are placed on a wafer support inside the reaction chamber. Both the wafer and support are heated to a desired temperature. In a typical wafer treatment step, reactant gases are passed over the heated wafer, causing the chemical vapor deposition (CVD) of a thin layer of the reactant material on the wafer. Various process conditions, particularly temperature uniformity and reactant gas distribution, must be carefully controlled to ensure the high quality of the resulting layers.
Through a series of deposition, doping, photolithography and etch steps, the starting substrate and the subsequent layers are converted into integrated circuits, with a single layer producing from tens to thousands or even millions of integrated devices, depending on the size of the wafer and the complexity of the circuits.
Batch processors have traditionally been employed in the semiconductor industry to allow multiple wafers to be processed simultaneously, thus economically presenting low processing times and costs per wafer. Recent advances in miniaturization and attendant circuit density, however, have lowered tolerances for imperfections in semiconductor processing. Accordingly, single wafer processing reactors have been developed for improved control of deposition conditions.
Among other process parameters, single wafer processing has greatly improved temperature and gas flow distribution across the wafer. In exchange for greater process control, however, processing time has become even more critical than with batch systems. Every second added to processing times must be multiplied by the number of wafers being processed serially, one at a time, through the same single-wafer processing chamber. Conversely, any improvements in wafer throughput can translate to significant fabrication cost savings.
One process for which process control is particularly critical, and for which single wafer processing is particularly useful, is the formation of epitaxial layers. If the deposited layer has the same crystallographic structure as the underlying silicon wafer, it is called an epitaxial layer. Through careful control of deposition conditions, reactant gases are passed over a heated substrate such that the deposited species precipitates in conformity with the underlying crystal structure, which is thus extended into the growing layer. The lowest level of devices, including transistors, often include epitaxial layers formed over a single crystal semiconductor substrate.
Cleanliness of the Interfaces Prior to Epitaxial Deposition
It is important that the epitaxial layers maintain a pure crystal structure, free of contamination which could affect device operation. The purity and crystalline structure of the underlying substrate prior to epitaxial deposition strongly affects the resultant epitaxial layer. Contaminants at the substrate surface, such as naturally forming “native oxide” and carbon contaminants, interfere with the crystal structure and consequent electrical properties of each overlying layer as it is formed, resulting in a polycrystalline layer. Note that clean, oxide-free surfaces are also desirable for a number of contexts other than epitaxial deposition.
Typically wafers are cleaned prior to deposition with an ammonium hydroxide, hydrogen peroxide mixture, known as an “APM” clean. The most popular cleaning methods involve one or more forms of an RCA cleaning procedure. The RCA Standard-Clean-1 (SC-1) procedure uses an APM solution and water heated to a temperature of about 70° C. The SC-1 procedure dissolves films and removes Group I and II metals. The Group I and II metals are removed through complexing with the reagents in the SC-1 solution. The RCA Standard-Clean-2 (SC-2) procedure utilizes a mixture of hydrogen peroxide, hydrochloric acid, and water heated to a temperature of about 70° C. The SC-2 procedure removes the metals that are not removed by the SC-1 procedure.
If an oxide-free surface is required, as in the case of epitaxial SiGe stacks, the silicon wafer is typically dipped into an aqueous solution of hydrofluoric acid or HF vapor treated to etch away the oxide layer left by an APM clean and, theoretically, obtain hydrogen termination. There are a large number of variations on RCA clean and hydrofluoric acid treatments. After cleaning, wafers are typically stored for a period of time before further processing. A native oxide tends to form on the previously oxide-free silicon wafer surface almost immediately after exposure to air or moisture. Further, silicon-fluorine and silicon-carbon bonds are often observed on the silicon wafer surface after cleaning. The fluorine and carbon contamination on the surface can be detrimental to the thermal budget and/or the quality of the layer to be grown or deposited on the surface of the wafer.
If the silicon wafer is dipped in hydrofluoric acid as the last cleaning step (also known as an “HF last” step), the surface of the silicon is typically terminated mostly with a monolayer of hydrogen, attached to the substrate largely through Si—H bonds. The hydrogen-terminated surface resists oxidation more than untreated silicon. If desired, the hydrogen termination can be removed at temperatures greater than about 500° C. However, the surface of a silicon wafer after a conventional HF last treatment normally starts to reoxidize within about 20 minutes after the original oxide layer was removed, quickly forming a new 5 Å to 7 Å thick oxide layer on the surface of the silicon wafer. Carbon or fluorine termination can better prevent re-oxidation, though this will introduce other problems, such as contamination or difficulty in removing the termination prior to subsequent processing. The problem of reoxidation after the HF last step has been detrimental to the high-throughput manufacturing of many silicon devices, but has been a particular hindrance in the creation of an epitaxial silicon emitter layer on top of a silicon germanium base.